`timescale 1ns/100ps
`default_nettype none

module tb_Odd_Colour_Space_Conv;

logic _Clock_50;
logic _resetn;

logic [31:0] _Y,_U,_V;

logic _start;

logic [31:0] _mulResult1;
logic [31:0] _mul1_Op1;
logic [31:0] _mul1_Op2;
logic [31:0] _mulResult2;
logic [31:0] _mul2_Op1;
logic [31:0] _mul2_Op2;
logic [31:0] _mulResult3;
logic [31:0] _mul3_Op1;
logic [31:0] _mul3_Op2;

logic [7:0] _R,_G,_B;
logic _finish;


Odd_Colour_Space_Conv uut (
    .CLOCK_50_I(_Clock_50),
    .resetn(_resetn),
    .Y(_Y),
    .U(_U),
    .V(_V),
    .start(_start),
    
    .mulResult1(_mulResult1),
    .mul1_Op1(_mul1_Op1),
    .mul1_Op2(_mul1_Op2),
    .mulResult2(_mulResult2),
    .mul2_Op1(_mul2_Op1),
    .mul2_Op2(_mul2_Op2),
    .mulResult3(_mulResult3),
    .mul3_Op1(_mul3_Op1),
    .mul3_Op2(_mul3_Op2), 


    .R(_R),
    .G(_G),
    .B(_B),
    .finish(_finish)
);

Mul32 mul321uut (
    .op1(_mul1_Op1),
    .op2(_mul1_Op2),
    .result(_mulResult1)
);
Mul32 mul322uut (
    .op1(_mul2_Op1),
    .op2(_mul2_Op2),
    .result(_mulResult2)    
);
Mul32 mul323uut (
    .op1(_mul3_Op1),
    .op2(_mul3_Op2),
    .result(_mulResult3) 
);

// Generate a 50 MHz clock
always begin
	# 10;
	_Clock_50 = ~_Clock_50;
end

task master_reset;
begin
	wait (_Clock_50 !== 1'bx);
	@ (posedge _Clock_50);
	_resetn = 1'b0;
	// Activate reset for 2 clock cycles
	@ (posedge _Clock_50);
	@ (posedge _Clock_50);	
	_resetn = 1'b1;	
end
endtask

task start_odd_colour_space_conv;
begin
    wait (_Clock_50 !== 1'bx);
    @ (posedge _Clock_50);
    _start = 1'b1;
    // Activate start for 1 clock cycles
	@ (posedge _Clock_50);
    _start = 1'b0;
end
endtask

// Initialize signals
initial begin
    _Clock_50 = 1'b0;
    _Y = 32'd131;
    _U = 32'd185;
    _V = 32'd168;
    
    // Apply master reset
    $write("Applying master reset...\n");
    master_reset;
    // Apply start signal
    $write("Giving start signal...\n");
    start_odd_colour_space_conv;

    @ (posedge uut.finish);
    $write("Odd_Conv is done. Expect 197  79  248.\n");
    @ (posedge _Clock_50);
    @ (posedge _Clock_50);
    $stop;
end

endmodule
